Bus control buffer amplifier
US6144257A · kind A · utility
9Cited by
9References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Feb 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a bus control buffer amplifier. The output terminal is associated with a first pull-down N-channel MOS transistor and with a second pull-up N-channel MOS transistor. The first N-channel MOS transistor is directly controlled by an input signal. The second MOS transistor is an N-channel transistor, and its gate is controlled by a third pull-down N-channel MOS transistor directly controlled by the input signal, and by a fourth pull-up N-channel MOS transistor, which is controlled by the inverted input signal. The fourth N-channel MOS transistor has a very abrupt drain-substrate junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.