Method and apparatus for implementing a serial memory architecture
US6144576A · kind A · utility
147Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.