Methods of erasing a memory device and a method of programming a memory device for low-voltage and low-power applications
US6144586A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Nov 7, 2000 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing and a method of programming a nonvolatile memory cell in a chip is disclosed. Said cell comprises a semiconductor substrate including a source and a drain region and a channel therebetween, a floating gate extending over a portion of said channel, a control gate extending over another portion of the channel region, and a program gate capacitively coupled through a dielectric layer to said floating gate. The methods or schemes are using substantially the lowest possible voltage to erase a nonvolatile memory cell of the floating-gate type without having the SILC problem. Therefore, these schemes are expected to allow a further scaling of the minimum feature size of Flash memory products which is necessary for cost reduction and density increase. The present invention also aims to further decrease the voltages necessary to erase/program the memory device without degrading the corresponding performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.