Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
US6146934A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.