Shallow trench isolation
US6146975A · kind A · utility
25Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jul 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.