Method and structure for uniform height solder bumps on a semiconductor wafer
US6146984A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1999 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Oct 8, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Uniform height solder bumps are created on a semiconductor wafer by exposing a dummy pattern of under bump metal for solder plating. The dummy pattern of exposed under bump metal follows the outer edge outline of a pattern of die that exists on the semiconductor wafer. The dummy pattern of under bump metal is exposed by removing a portion of a layer of photoresist that is deposited over the under bump metal. The dummy pattern of under bump metal is exposed on the wafer at the same time that under bump metal above the contact pads is exposed. Solder material is then plated onto the exposed under bump metal that exists above the contact pads and in the dummy pattern. The dummy pattern of exposed under bump metal around the outer edge of the die pattern causes current crowding to occur primarily at the dummy pattern of exposed under bump metal instead of at the contact pads that are on die at the outer edge of the die pattern. Because current crowding occurs primarily at the dummy pattern of exposed under bump metal instead of at the exposed under bump metal above the contact pads of the outer edge die, the plating current density across the die pattern is more uniform, thereby produc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.