Compliant multichip package
US6147401A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 2000 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Feb 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip package includes a substrate including a plurality of conductive traces and flexible leads connected to outer ends of at least some of the conductive traces adjacent the periphery of said flexible substrate, the substrate including conductive terminals accessible at a surface thereof connected to at least some of the traces. The package includes a first microelectronic element having a front face including contacts and a back face, the front face of the first microelectronic element confronting the flexible substrate. The package also includes a second microelectronic element larger than the first microelectronic element, the second microelectronic element having a front face including contacts, the second microelectronic element overlying the first microelectronic element with the front face of the second microelectronic element facing toward the substrate. A compliant element is disposed alongside the first microelectronic element between the second microelectronic element and the substrate. The flexible leads are connected to the second microelectronic element and at least some of the traces are connected to the first microelectronic element for electrically intercon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.