Redundancy method and structure for 2-bit non-volatile memory cells
US6147904A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy method and structure for 2-bit non-volatile memory cells formed in a memory array. The 2-bit memory transistors are arranged to form bit locations, each bit location including eight charge trapping regions. An initial charge trapping region is addressed during program (write) and read operations directed to the bit location, with seven redundant charge trapping regions being maintained in an erased state. At a predefined time, such as when operation of the initial charge trapping region declines due to repeated use, one of the redundant charge trapping regions replaces the initial charge trapping region, and is addressed during program (write) and read operations directed to the bit location. Redundancy data is stored in a supplemental non-volatile memory location of the memory array. The redundancy data identifies a currently-used charge trapping region of a bit location, and instructs addressing circuitry to store bit data addressed to that bit location in the currently-used charge trapping region. After a charge trapping region performance is used (i.e., when performance declines), the redundancy data is updated such that bit data addressed to the bit location is st…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.