Scalable computer system
US6148356A · kind A · utility
24Cited by
20References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jan 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.