Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes
US6148375A · kind A · utility
6Cited by
7References
3Claims
0Family size
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Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest level of cache memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.