Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6148380A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1997 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jan 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.