Shared floating-point unit in a single chip multiprocessor
US6148395A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1997 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | May 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip multiprocessor (2, 102) is disclosed. The multiprocessor (2, 102) includes multiple central processing units, or CPUs, (10, 110) that share a floating-point unit (5, 105). The floating-point unit (5, 105) may receive floating-point instruction codes from either or both of the multiple CPUs (10, 110) in the multiprocessor (2, 102), and includes circuitry (52) for decoding the floating-point instructions for execution by its execution circuitry (65). A dispatch unit (56) in the floating-point unit (5, 105) performs arbitration between floating-point instructions if more than one of the CPUs (10, 110) is forwarding instructions to the floating-point unit (5, 105) at the same time. Dedicated register banks, preferably in the form of stacks (60), are provided in the floating-point unit (5, 105). The disclosed multiprocessor (2, 102) provides efficiency in allowing sharing of the floating-point unit (5, 105) by the multiple CPUs (10, 110), considering that the utilization of a floating-point unit (5,105) by a single CPU (10, 110) is generally relatively low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.