Method of manufacturing a shallow trench isolation structure for a semiconductor device
US6150072A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 22, 1997 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Aug 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a shallow trench isolation structure involves several steps. The steps of an illustrative method include forming a first resist pattern on a substrate, etching the substrate to form a shallow trench therein using the first resist pattern as a mask, removing the first resist pattern from the substrate, depositing an oxide layer on the substrate including in the shallow trench, depositing a polish stop layer on the oxide layer, forming a second resist pattern on a portion of the polish stop layer substantially covering the shallow trench using the same mask as the mask for the first resist pattern, etching the polish stop layer, removing the second resist pattern leaving the portion of the polish stop layer substantially covering the shallow trench, polishing the oxide layer using the portion of the polish stop layer substantially covering the shallow trench as a polish stop, and removing the portion of the polish stop layer substantially covering the shallow trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.