Shallow trench isolation method utilizing combination of spacer and fill
US6150212A · kind A · utility
45Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Jul 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0387
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.