Avoiding abnormal capacitor formation by an offline edge-bead rinsing (EBR)

US6150215A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Kuo-Chi Lin · New Taipei, TW
• Da-Wen Hsia · Taipei, TW

Key dates

• Filing date: Aug 10, 1999
• Grant date: Nov 21, 2000
• Expiry date: Aug 10, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A method for ensuring no capacitor peeling at the edge of a wafer in the fabrication of dynamic random access memory (DRAM) is disclosed. The method includes first providing a semiconductor substrate having a semiconductor structure formed thereon. A dielectric layer is then formed overlying the semiconductor structure, and patterned for defining a contact window. Followed by, the deposition of a silicon layer over the dielectric layer that fills up the contact window. Consequentially, a photoresist layer is coated overlying the silicon layer, where it will be rinsed twice by a combination of an online EBR (and/or a WEE) and an offline EBR at a distance inwardly away from the edge of the wafer in process for removing a portion of the photoresist to avoid abnormal capacitor formation in later stages. Then, a photolithography process is carried out against the photoresist layer to form a photoresist mask. Finally, the silicon layer is etched where it is not covered by the photoresist mask to form a lower capacitor electrode. The photoresist mask is stripped as to conclude the present invention.