Method for forming self-aligned features
US6150256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.