Combination test structures for in-situ measurements during fabrication of semiconductor devices
US6150669A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.