Semiconductor integrated circuit device and method for manufacturing the same
US6150689A · kind A · utility
66Cited by
10References
18Claims
0Family size
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Key dates
| Filing date | Jan 13, 1997 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Jan 13, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
Abstract
The sheet resistance of a gate electrode 8A (a word line) of memory cell selection MISFET Q of a DRAM and a sheet resistance of bit lines BL.sub.1, BL.sub.2 are, respectively, 2 .OMEGA./.quadrature. or below. Interconnections of a peripheral circuit are formed during the step of forming the gate electrode 8A (the word line WL) or the bit lines BL.sub.1, BL.sub.2 by which the number of the steps of manufacturing the DRAM can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.