Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification
US6150807A · kind A · utility
10Cited by
21References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new circuit architecture is provided for testing digital integrated circuits which allows one to arbitrarily force any combination of logic values to be simultaneously driven onto any combination of internal nets. This allows all of the connections to each internal logic cell, and the logic cell itself, to be verified by applying a set of test patterns to each logic cell individually. In this way, the integrity of the entire device can be verified without having knowledge of the operation of the circuit as a whole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.