NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors
US6151249A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1994 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.