JFET transistor manufacturing method
US6153453A · kind A · utility
17Cited by
2References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-type channel region at the same time as lightly-doped drain/source regions of the P-channel MOS transistors of; forming an N-type gate region at the same time as lightly-doped drain/source regions of the N-channel MOS transistors; and forming P-type drain/source regions at the same time as heavily-doped drain/source regions of P-channel MOS transistors of channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.