Method for fabricating a flash memory
US6153472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Feb 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A method for fabricating a flash memory is provided. The method contains sequentially forming a tunneling oxide layer, a polysilicon layer, and a silicon nitride layer on a semiconductor substrate. Patterning the silicon nitride layer, polysilicon layer, the tunneling oxide layer, and the substrate forms a trench in the substrate. A shallow trench isolation (STI) structure is formed to fill the trench up the silicon nitride layer. The silicon nitride layer is removed to expose the polysilicon layer and a portion of each sidewall of the STI structure. A polysilicon spacer is formed on each exposed sidewall of the STI structure. An upper portion of the STI structure is removed so as to expose a portion of each sidewall of the polysilicon layer. The polysilicon layer serves as a floating gate. A conformal dielectric layer and a top polysilicon layer are formed over the substrate. The top polysilicon layer, the dielectric layer, and the polysilicon layer are patterned to form a strip control gate, which covers the floating gate, that is a remaining portion of the polysilicon layer on the tunneling oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.