Method of fabricating a dual damascene structure
US6153528A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1047
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a dual damascene structure is provided. The method contains providing a substrate, which has a patterned metal layer on it. A first liner oxide layer, a first seed layer are sequentially formed over the substrate. The first seed layer is patterned to form a first opening above the patterned metal layer to expose the first liner oxide layer. A first dielectric layer is formed over the substrate. The first dielectric layer includes a first porous dielectric layer on the first seed layer, and a first normal dielectric layer on the exposed portion of the first liner oxide layer. A first cap layer is formed over the first dielectric layer, and is planarized. An etching stop layer with a second opening above the first opening to expose the first cap layer is formed on the first cap layer. With the same formation mechanism, a second liner oxide layer, a second seed layer with a third opening above the second opening, a second porous dielectric layer, a second cap layer are formed over the substrate. A mask layer is formed over the second cap layer. Patterning the above layers forms a damascene opening in the first normal dielectric layer and the second normal diel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.