Vertical DRAM cell with wordline self-aligned to storage trench
US6153902A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A dynamic random access memory (DRAM) device. The DRAM device is formed in a substrate having a top surface and a trench with a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.