Processor employing multiple register sets to eliminate interrupts
US6154832A · kind A · utility
24Cited by
7References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other (non-interrupt) tasks. The interrupt sources may record interrupt service requests instead of signalling an interrupt to the processor. Periodically, the processor may poll the interrupt sources to determine if a service request is recorded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.