Debug interface including state machines for timing synchronization and communication
US6154856A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Mar 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for debugging a processor includes logic circuits for communicating commands and data between a serial input/output port, a trace logic, and the processor. Some embodiments of the debugging system also include a parallel input/output port so that the logic circuits also communicate commands and data between the parallel input/output port, the trace logic, and the processor. The debug system includes a plurality of state machines that read the commands and data from the serial input/output ports. The commands are decoded by a decode logic. Some of the commands, such as commands for reading data from memory, utilize processor intervention and are transferred to the processor for execution. The state machines operate only on a single command at one time so that an active state machine does not accept additional commands until completion of the command that is currently executed. Once execution of the command is complete, the state machines generate an indication of the completion event or condition, typically by setting a flag in a debug register or by asserting a readable output pin. The completion event or condition is accessed by a debug tool such as a host processor, a mo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.