Method and apparatus for built-in self-test of smart memories
US6154861A · kind A · utility
6Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.