EEPROM device manufacturing method
US6156609A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Apr 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.