Patent · US Expired

Method for fabricating direct wafer bond Si/SiO.sub.2 /Si substrates

US6156621A · kind A · utility

5Cited by

4References

8Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Paul Nance · Sunnyvale, US
Ludwig Leipold · Munich, DE
Wolfgang Werner · Hersbruck, DE

Key dates

Filing date	Sep 22, 1998
Grant date	Dec 5, 2000
Priority date	—
Expiry date	Sep 22, 2018

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/977
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating direct wafer bond Si/SiO.sub.2 /Si substrates in which trenches are etched into a rear side of a device wafer. Subsequently, the rear side of the device wafer is ground. The device wafer is then placed by its front side onto the carrier wafer and the wafers are cross-linked to each other. The method has the advantage that a trench depth is no longer defined by an inaccurate etching process but rather by a thinning-back process that can be precisely controlled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.