Circuit for providing a reading phase after power-on-reset
US6157579A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Apr 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output signal that is supplied to another input of the comparator. The reference voltage signal reaches its steady operational value before the supply voltage, and the output signal has the same linear pattern as the supply voltage with a different angular coefficient. The comparator outputs a control signal for starting the first reading phase of the memory device. In one preferred embodiment, the memory device has a single power supply and a zero consumption standby mode. Additionally, there is provided a method for providing a first reading phase after a Power-On-Reset in a memory device. According to the method, a reference voltage signal and a proportional voltage signal are generated and compared so as to generate a control signal for starting the first reading phase of the memory device. The generated reference voltage signal reaches its steady operational value before the supply voltage, and the genera…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.