Method of manufacturing semiconductor device comprising high voltage regions and floating gates
US6159799A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
A method of manufacturing a semiconductor device includes the steps of preparing a substrate having a high-voltage applied region, a peripheral region, a cell region with at least first and second portions, the high-voltage applied region having a well formed therein; simultaneously forming a plurality of spaced floating gates on the first and second portions of the cell region and a plurality of spaced first gates on the high-voltage applied region; implanting first impurity ions in the high-voltage applied region of the substrate using the first gates as a mask to form a first impurity region, the floating gates masking the cell region from the first impurity ions; simultaneously forming control gates on the respective floating gates of the cell region and a plurality of spaced second gates on the peripheral region; selectively etching one of the control gates and one of the floating gates to form a plurality of gate patterns in the first portion of the cell region; and implanting second impurity ions in the substrate at sides of the gate patterns and at sides of the first gates to simultaneously form second impurity regions at sides of the gate patterns and twice implanted first…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.