Method of fabricating landing pad
US6159843A · kind A · utility
3Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer is formed to cover the gate. Using an oxygen based etchant to performed an isotropic chemical dry etching on the polysilicon layer, the polysilicon layer is planarized until a part of the spacer is exposed. The polysilicon layer is patterned to form a landing pad in contact with the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.