Chingfu Lin
14Patents
5h-index
9Co-inventors
51Inventor score
Filing activity: Nov 30, 1998 → Feb 3, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6261921A | Method of forming shallow trench isolation structure | Electricity | 78 | Expired |
| US6162679A | Method of manufacturing DRAM capacitor | Electricity | 12 | Expired |
| US7273808B1 | Reactive barrier/seed preclean process for damascene process | Electricity | 11 | Expired |
| US6232184A | Method of manufacturing floating gate of stacked-gate nonvolatile memory unit | Electricity | 9 | Expired |
| US6930038B2 | Dual damascene partial gap fill polymer fabrication process | Electricity | 6 | Expired |
| US6277742A | Method of protecting tungsten plug from corroding | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6221734A | Method of reducing CMP dishing effect | Electricity | 4 | Expired |
| US6399506B2 | Method for planarizing an oxide layer | Electricity | 4 | Expired |
| US6350681B1 | Method of forming dual damascene structure | Electricity | 4 | Expired |
| US6245667A | Method of forming via | Electricity | 3 | Expired |
| US6159843A | Method of fabricating landing pad | Electricity | 3 | Expired |
| US6207545A | Method for forming a T-shaped plug having increased contact area | Electricity | 1 | Expired |
| US6162732A | Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM | Emerging Cross-Sectional Technologies | 1 | Expired |
| US6277741A | Method and planarizing polysilicon layer | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.