Enhanced heat dissipating chip scale package method and devices
US6160311A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhanced heat dissipating Chip Scale Package (CSP) method and devices include preparing a heat dissipating base with a recess surrounded by a guarding wall. A chip with an integrated circuit (IC) layout is adhered the heat dissipating base in the recess. A substrate with a metallic circuit layer that is smaller size than the chip is then adhered to the chip. Then coupling the metallic circuit layer with the IC layout. A non-conductive resin is then filled in the recess within the guarding wall and covers the coupling portion. The resulting package device produced by means of BGA package process is small size and has enhanced heat dissipating property. The Package size/chip size ratio may be lower than 1.2 to meet the CSP requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.