Instruction cache for multithreaded processor
US6161166A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Mar 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit. In this case, the full real address of the desired instruction can be constructed from the effective address and the ERAT, making it unnecessary to access slower address translation mechanisms for main memory. Because there is a separate line fill sequencer for each thread, threads are independently able to sati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.