Patent · US Expired

Pattern generator for a semiconductor integrated circuit tester

US6161206A · kind A · utility

14Cited by
10References
31Claims
0Family size

Assignee

Inventor

Key dates

Filing dateApr 30, 1998
Grant dateDec 12, 2000
Priority date—
Expiry dateApr 30, 2018

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/1044
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A test pattern generator for a semiconductor integrated circuit tester comprises a DRAM for receiving and storing test pattern data in blocks and a SRAM for storing checking data in units, wherein each unit of checking data stored in the SRAM bears a predetermined relationship to a corresponding block received by the DRAM. A DRAM sequencer addresses the DRAM for reading the blocks of test pattern data in a predetermined order and a SRAM sequencer addresses the SRAM for reading the units of checking data from the SRAM. A validating circuit receives a block of test pattern data read from the DRAM and the corresponding unit of checking data read from the SRAM and provides an output which indicates whether the unit of checking data is in the predetermined relationship with the block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.