Process for sort testing C4 bumped wafers
US6162652A · kind A · utility
114Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of testing an integrated circuit device including depositing a solder bump on a surface of a bond pad on an integrated circuit device, heat treating the solder bump, and testing the integrated circuit device by probing the solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.