Method of manufacturing DRAM capacitor
US6162679A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming trench type DRAM capacitor. An insulation layer is formed on a substrate with a trench exposing a conductive region of the substrate. A first conductive layer is formed and conformal to a surface profile of the substrate. A photoresist layer is formed over the first conductive layer to fill the trench. A three-stage of etching process is carried out. A first stage of etching step is carried out to remove a portion of the photoresist layer, thereby exposing the first conductive layer. A second stage step is carried out to remove the first conductive layer by performing an isotropic dry etching step. The first conductive layer is slightly over-etched so that a portion of the first conductive layer inside the trench is also removed. Therefore, the first conductive layer inside the trench will be at a distance lower than a top surface of the insulation layer. A third stage of etching operation is carried out to remove the remaining photoresist layer so that the remaining first conductive layer inside the trench is exposed. A dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.