Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications
US6162728A · kind A · utility
20Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Sep 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming copper interconnect lines using a damascene process. After the formation of the copper seed layer (112) and prior to the formation of the copper layer (120), a pattern (114) is formed to block the formation of the copper in non-interconnect areas. The copper layer (120) is then formed and the pattern (114) is removed. The exposed seed layer (112) and any barrier layers (110) thereunder are removed. Finally, the copper layer (120) is chemically-mechanically polished
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.