Inventor · Garland, TX, US

Alwin Tsao

25Patents
9h-index
36Co-inventors
75Inventor score

Filing activity: Dec 8, 1998 → Jul 31, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US8067279B2 Application of different isolation schemes for logic and embedded memory Electricity 114 Active
US7141480B2 Tri-gate low power device and method for manufacturing the same Electricity 43 Expired
US6143594A On-chip ESD protection in dual voltage CMOS Electricity 26 Expired
US6162728A Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications Electricity 20 Expired
US6693357B1 Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity Electricity 17 Expired
US6137144A On-chip ESD protection in dual voltage CMOS Electricity 16 Expired
US7274046B2 Tri-gate low power device and method for manufacturing the same Electricity 11 Expired
US7250334B2 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode Electricity 10 Expired
US6211769A System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flow Electricity 10 Expired
US7045436B2 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) Electricity 9 Expired
US7193277B2 Application of different isolation schemes for logic and embedded memory Electricity 4 Expired
US6333238A Method for minimizing the temperature coefficient of resistance of passive resistors in an integrated circuit process flow Electricity 4 Expired
US7141468B2 Application of different isolation schemes for logic and embedded memory Electricity 3 Expired
US9202859B1 Well resistors and polysilicon resistors Electricity 2 Active
US7314800B2 Application of different isolation schemes for logic and embedded memory Electricity 2 Expired
US9245755B2 Deep collector vertical bipolar transistor with enhanced gain Electricity 1 Active
US7662688B2 Application of different isolation schemes for logic and embedded memory Electricity 1 Active
US9431248B2 High tilt angle plus twist drain extension implant for CHC lifetime improvement Electricity 0 Active
US8753938B2 Method for 1/F noise reduction in NMOS devices Electricity 0 Active
US9397164B2 Deep collector vertical bipolar transistor with enhanced gain Electricity 0 Active
US9379176B2 Well resistors and polysilicon resistors Electricity 0 Active
US11455452B2 Variable implant and wafer-level feed-forward for dopant dose optimization Electricity 0 Active
US7199011B2 Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon Electricity 0 Expired
US8653607B2 Method for 1/F noise reduction in NMOS devices Electricity 0 Active
US9177802B2 High tilt angle plus twist drain extension implant for CHC lifetime improvement Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.