Temperature compensated delay chain
US6163195A · kind A · utility
21Cited by
6References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 26, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00202
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit is provided for delaying signals. The delay circuit includes: at least one inverter having a time delay; at least one current source coupled to the at least one inverter, the at least one current source providing charging current to the at least one inverter; and a voltage biasing circuit coupled to the at least one current source, the voltage biasing circuit providing a biasing voltage to the at least one current source such that the at least one current source varies the charging current so as to maintain the time delay of the at least one inverter substantially constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.