David Jefferson
64Patents
21h-index
47Co-inventors
88Inventor score
Filing activity: Nov 16, 1992 → Aug 21, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6215326A | Programmable logic device architecture with super-regions having logic regions and a memory region | Electricity | 263 | Expired |
| US5744991A | System for distributing clocks using a delay lock loop in a programmable logic circuit | Electricity | 180 | Expired |
| US5963069A | System for distributing clocks using a delay lock loop in a programmable logic circuit | Electricity | 104 | Expired |
| US6107820A | Redundancy circuitry for programmable logic devices with interleaved input circuits | Electricity | 94 | Expired |
| US6130552A | Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution | Electricity | 88 | Expired |
| US5642082A | Loop filter level detection circuit and method | Electricity | 76 | Expired |
| US5699020A | Phase latched differential charge pump circuit and method | Emerging Cross-Sectional Technologies | 74 | Expired |
| US5847617A | Variable-path-length voltage-controlled oscillator circuit | Electricity | 68 | Expired |
| US6292016A | Programmable logic with on-chip DLL or PLL to distribute clock | Electricity | 68 | Expired |
| US5977793A | Programmable logic device with hierarchical interconnection resources | Electricity | 66 | Expired |
| US5850152A | Programmable logic array integrated circuit devices | Electricity | 60 | Expired |
| US6326812A | Programmable logic device with logic signal delay compensated clock network | Electricity | 45 | Expired |
| US5850151A | Programmable logic array intergrated circuit devices | Electricity | 43 | Expired |
| US6127865A | Programmable logic device with logic signal delay compensated clock network | Electricity | 42 | Expired |
| US7725738B1 | FPGA configuration bitstream protection using multiple keys | Electricity | 41 | Active |
| US7606362B1 | FPGA configuration bitstream encryption using modified key | Electricity | 32 | Active |
| US5293623A | Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading | Physics | 31 | Expired |
| US6417694B1 | Programmable logic device with hierarchical interconnection resources | Electricity | 24 | Expired |
| US6965249B2 | Programmable logic device with redundant circuitry | Electricity | 24 | Expired |
| US7818584B1 | One-time programmable memories for key storage | Electricity | 22 | Active |
| US7734043B1 | Encryption key obfuscation and storage | Electricity | 21 | Active |
| US6163195A | Temperature compensated delay chain | Electricity | 21 | Expired |
| US6300794A | Programmable logic device with hierarchical interconnection resources | Electricity | 19 | Expired |
| US6826741B1 | Flexible I/O routing resources | Electricity | 14 | Expired |
| US6600337B2 | Line segmentation in programmable logic devices having redundancy circuitry | Physics | 14 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.