Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed
US6163483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.