Semiconductor memory having multiple redundant columns with offset segmentation boundaries
US6163489A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.