Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
US6163840A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.