On-chip test circuit for evaluating an on-chip signal using an external test signal
US6163862A · kind A · utility
434Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.