Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer

US6165830A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventors

• Dahcheng Lin
• Jung-Ho Chang · Taipei, TW
• Hsi-Chuan Chen · Hsinchu, TW

Key dates

• Filing date: Nov 2, 1998
• Grant date: Dec 26, 2000
• Expiry date: Nov 2, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG silicon layer, on a doped amorphous silicon, storage node shape, with the HSG silicon layer supplying increased surface area, and thus increased capacitance, for the DRAM capacitor. A doped polysilicon layer, selectively deposited on the underlying HSG silicon layer, supplies additional dopant to the HSG silicon layer, residing on the doped amorphous silicon, storage node shape, thus minimizing a capacitance depletion phenomena, that can be present with lightly doped storage node structures.