Clock synchronous type semiconductor memory device that can switch word configuration
US6166989A · kind A · utility
50Cited by
1References
29Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 3, 1999 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Mar 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.