Methods and apparatus for automatically generating interconnect patterns in programmable logic devices
US6167364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Sep 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines. Where all of the modeled delay data are within an error limit of corresponding measured delay data, the estimated circuit parameters are designated as the circuit parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.