Inventor · Los Altos, CA, US

David Karchmer

27Patents
8h-index
29Co-inventors
71Inventor score

Filing activity: Sep 26, 1995 → Oct 11, 2013

Most-cited inventions

PatentTitleAreaCited byStatus
US6026226A Local compilation in context within a design hierarchy Emerging Cross-Sectional Technologies 99 Expired
US6167364A Methods and apparatus for automatically generating interconnect patterns in programmable logic devices Physics 52 Expired
US7669157B1 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Physics 20 Active
US7784008B1 Performance visualization system Physics 17 Active
US7275232B2 Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits Physics 17 Expired
US7584443B1 Clock domain conflict analysis for timing graphs Physics 15 Active
US6173245A Programmable logic array device design using parameterized logic modules Physics 15 Expired
US6697773B1 Using assignment decision diagrams with control nodes for sequential review during behavioral simulation Physics 14 Expired
US8112728B1 Early timing estimation of timing statistical properties of placement Physics 8 Active
US7464362B1 Method and apparatus for performing incremental compilation Physics 8 Active
US7853911B1 Method and apparatus for performing path-level skew optimization and analysis for a logic design Physics 7 Active
US7231337B1 Using assignment decision diagrams with control nodes for sequential review during behavioral simulation Physics 5 Expired
US6961690B1 Behaviorial digital simulation using hybrid control and data flow representations Physics 4 Expired
US8572530B1 Method and apparatus for performing path-level skew optimization and analysis for a logic design Physics 4 Active
US5768562A Methods for implementing logic in auxiliary components associated with programmable logic array devices Physics 4 Expired
US8516504B1 Method for adding device information by extending an application programming interface Physics 4 Expired
US7064580B2 Mask-programmable logic device with programmable portions Electricity 4 Expired
US8250505B1 Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Physics 4 Active
US7725856B1 Method and apparatus for performing parallel slack computation Physics 4 Active
US7358766B2 Mask-programmable logic device with programmable portions Electricity 4 Active
US7877721B2 Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits Physics 3 Active
US7577929B1 Early timing estimation of timing statistical properties of placement Physics 3 Active
US7587688B1 User-directed timing-driven synthesis Physics 2 Active
US8161469B1 Method and apparatus for comparing programmable logic device configurations Physics 2 Active
US8589838B1 M/A for performing incremental compilation using top-down and bottom-up design approaches Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.